Method for producing SOI wafer and SOI wafer

ABSTRACT

A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

TECHNICAL FIELD

The present invention relates to a method for producing an SOI (SiliconOn Insulator) wafer, more specifically, a method for producing an SOIwafer by the so-called hydrogen ion delamination method (also calledSmart Cut Method (registered trademark)) comprising bonding anion-implanted wafer to another wafer that serves as a substrate and thendelaminating the wafers to produce an SOI wafer, in which surfaceroughness is improved by a heat treatment after the delamination, and anSOI wafer produced by the method. Further, the present invention alsorelates to a method for producing an SOI wafer that can reduce bondingfailures during the production of the SOI wafer and can provide SOIwafers with good yield, in which a heat treatment is performed after thedelamination.

BACKGROUND ART

Recently, as a method for producing an SOI wafer, the method comprisingbonding a wafer implanted with hydrogen ions or the like and thendelaminating the wafer to produce an SOI wafer (a technique calledhydrogen ion delamination method: Smart Cut Method (registeredtrademark)) is newly coming to attract much attention. This method is atechnique for producing an SOI wafer, wherein an oxide layer is formedon at least one of two silicon wafers, at least either hydrogen ions orrare gas ions are implanted into one wafer from its top surface to forma micro bubble layer (enclosed layer) in this silicon wafer, then theion-implanted surface of the wafer is bonded to the other silicon wafervia the oxide layer, thereafter the wafers were subjected to a heattreatment (delamination heat treatment) to delaminate one of the waferas a thin film at the micro bubble layer as a cleavage plane, and theother wafer is further subjected to a heat treatment (bonding heattreatment) to obtain an SOI wafer in which an SOI layer is firmly bondedon the silicon wafer (refer to Japanese Patent Laid-open (Kokai)Publication No. 5-211128).

When an SOI wafer is produced by the hydrogen ion delamination method,the SOI layer surface as it is after the delamination at the microbubble layer as a cleavage plane has higher surface roughness comparedwith a mirror-polished wafer used for usual device production, andtherefore the wafer as it is cannot be used for the device production.Accordingly, in order to improve the aforementioned surface roughness,polishing using a small amount of stock removal for polishing, which iscalled touch polish, is usually performed.

However, the SOI layer is extremely thin, and therefore when its surfaceis polished, there is caused a problem that variation in SOI layerthickness becomes large due to fluctuation of the polishing amountwithin the surface.

Therefore, it was proposed to improve the surface roughness by a heattreatment of the SOI layer surface immediately after the delamination,without using polishing.

Japanese Patent Laid-open (Kokai) Publication No. 10-242154 discloses amethod wherein, after a second heat treatment for strengthening bondingof a support substrate and a single crystal silicon thin film (bondingheat treatment), a third heat treatment is performed at a temperature of1000— 1300° C. for 10 minutes to 5 hours in a hydrogen atmosphere toimprove average surface roughness of the silicon thin film.

Further, Japanese Patent Laid-open (Kokai) Publication No. 10-275905discloses a method for producing an SOI wafer wherein a wafer of the SOIstructure having a delaminated surface, which is obtained by thehydrogen ion delamination method, is subjected to annealing in ahydrogen atmosphere (hydrogen annealing) to flatten the delaminatedsurface.

Thus, any of the techniques disclosed in the aforementioned patentdocuments utilizes a heat treatment in a hydrogen atmosphere to improvethe surface roughness of a delaminated wafer.

The aforementioned Japanese Patent Laid-open (Kokai) Publication No.10-242154 defines temperature and time for the third heat treatment(hydrogen annealing) for improving the average surface roughness.However, if, for example, the SOI layer (single crystal silicon thinfilm) is formed from a wafer produced by the Czochralski method (CZmethod) and it has a small thickness of about 0.5 μm or less, there iscaused a problem that a buried oxide layer is etched by hydrogen gaspenetrated through COP (Crystal Originated Particle), which is avoid-like grown-in defect, when the hydrogen annealing is performed.Further, although it is known that a heat treatment performed in anargon atmosphere also improves the surface roughness like the heattreatment in hydrogen, however, it also cannot obviate the problem ofetching through COP. That is, it is known that a CZ wafer has crystaldefects called COPs introduced therein during the crystal growth, and ithas become clear that, if such a CZ wafer is utilized for the bond waferto be a device active layer, COPs exist also in the SOI layer and in acase of an extremely thin SOI layer, which is required in recent years,the COPs penetrate the SOI layer and form pinholes to markedly degradeelectric characteristics.

Meanwhile, Japanese Patent Laid-open (Kokai) Publication No. 10-275905discloses that, as specific methods for the heat treatment (annealing),the heat treatment can be performed by any one of short time annealing(rapid thermal anneal, RTA) of the single wafer processing in whichwafer is treated one by one and plasma annealing, besides the method ofhydrogen annealing performed for several tens of seconds to several tensof minutes in a hydrogen atmosphere using a batch processing typefurnace.

Among the aforementioned various heat treatments (annealing), the rapidthermal annealing (RTA) utilizing a rapid heating/rapid coolingapparatus can be performed within an extremely short period of time.Therefore, it was considered that the aforementioned buried oxide layerwas not etched, COPs in the SOI layer could be eliminatedsimultaneously, and thus the surface roughness could be improvedefficiently.

However, when the inventors of the present invention preciselyinvestigated the improvement of the surface roughness of SOI wafer byRTA, it was found that it was only short period components of surfaceroughness that were improved to a level comparable to that ofmirror-polished wafers for the usual device production, and long periodcomponents were still extremely inferior to those of the mirror-polishedwafers.

When the relationship between the heat treatment time and the surfaceroughness was further investigated, it was found that, in order toimprove the long period components of surface roughness by an RTAapparatus, a heat treatment of high temperature for long period of time(for example, at 1225° C. for 3 hours or more) was required.

However, since the heat treatment performed by an RTA apparatus is oneof the single wafer processing type, treatment for a long period of timelowers throughput and degrades efficiency. In addition, it increases theproduction cost. Therefore, it is not practical.

On the other hand, although a batch processing furnace that enables aheat treatment for a long period of time can treat a lot of wafers atone time, it suffers from a problem that the buried oxide layer isetched through COPs in the SOI layer during the hydrogen annealingtreatment to form pits due to the slower temperature increasing rate.

DISCLOSURE OF THE INVENTION

The present invention was accomplished in order to solve theaforementioned problems, and its object is to improve surface roughnessover the range from short period to long period of an SOI layer surfacedelaminated by the hydrogen ion delamination method without polishingand to secure its thickness uniformity, as well as to efficientlyproduce SOI wafers free from generation of pits due to COPs in SOIlayers with high throughput.

In order to achieve the aforementioned object, the present inventionprovides a method for producing an SOI wafer by the hydrogen iondelamination method comprising at least a step of bonding a base waferand a bond wafer having a micro bubble layer formed by gas ionimplantation and a step of delaminating a wafer having an SOI layer atthe micro bubble layer as a border, wherein, after the delaminationstep, the wafer having an SOI layer is subjected to a two-stage heattreatment in an atmosphere containing hydrogen or argon utilizing arapid heating/rapid cooling apparatus and a batch processing typefurnace.

If a wafer having an SOI layer is subjected to a heat treatmentconsisting of two stages utilizing separately a rapid heating/rapidcooling apparatus and a batch processing type furnace after thedelamination as described above, surface crystallinity is restored andthe surface roughness of short periods is improved in the heat treatmentby the rapid heating/rapid cooling apparatus, and the surface roughnessof long periods can be improved by the heat treatment utilizing thebatch processing type furnace. Further, since a plurality of wafers canbe subjected to a heat treatment at one time in the batch processingtype furnace, the wafers can be produced with higher throughput comparedwith a case where wafers are subjected to a heat treatment for a longperiod of time by the single wafer processing in a rapid heating/rapidcooling apparatus.

Furthermore, since this method does not use polishing such as touchpolishing, thickness uniformity of the SOI layer is also secured.

Further, in the aforementioned method, the two-stage heat treatment ispreferably performed by subjecting the wafers to a heat treatment in therapid heating/rapid cooling apparatus and then a heat treatment in thebatch processing type furnace.

In the present invention, both of the short period components and longperiod components of surface roughness are improved by the two-stageheat treatment as described above. If the heat treatment in the rapidheating/rapid cooling apparatus for a short period of time is performedas the first stage, crystallinity of the surface is restored and COPs inthe SOI layer are markedly reduced. Therefore, when the heat treatmentby the batch processing type furnace is performed in a subsequent stage,COPs in the SOI layer are substantially eliminated already. Accordingly,even if the heat treatment is performed for a relatively long period oftime, the etching of the buried oxide layer by hydrogen gas or argongas, which is caused through penetrated COPs, is suppressed, and thuspits are not generated.

Further, the present invention also provides a method for producing anSOI wafer by the hydrogen ion delamination method comprising at least astep of bonding a base wafer and a bond wafer having a micro bubblelayer formed by gas ion implantation and a step of delaminating a waferhaving an SOI layer at the micro bubble layer as a border, wherein an FZwafer, an epitaxial wafer or a CZ wafer of which COPs at least onsurface are reduced is used as the bond wafer, and the wafer having anSOI layer is subjected to a heat treatment under an atmospherecontaining hydrogen or argon in a batch processing type furnace afterthe delamination step.

If an SOI wafer is produced by using any one of an FZ wafer, anepitaxial wafer and a CZ wafer of which COPs at least on surface arereduced is used as the bond wafer as described above, COPs in the SOIlayer can be reduced or substantially completely eliminated. Therefore,the problem of etching of the buried oxide layer due to COPs is notcaused, and a heat treatment at a high temperature for a long period oftime in a batch processing type furnace also becomes possible.

Further, another object of the present invention is to provide SOIwafers with good yield by reducing bonding failures such as voids andblisters generated at a bonding surface, when SOI wafers of which COPsin the SOI layer are reduced are produced as described above.

To this end, the present invention also provides a method characterizedby using a CZ wafer produced from a single crystal ingot of which COPsare reduced for the whole crystal as a wafer used for the bond wafer.

If a CZ wafer produced from a single crystal ingot of which COPs arereduced for the whole crystal is used as described above, a usualmirror-polished surface can be used as a bonding surface, and thereforebonding failures can be reduced compared with a case utilizing anepitaxial wafer. Further, since the method utilizes a CZ wafer, it canbe applied to a wafer having a large diameter such as 200 mm, 300 mm ora further larger diameter, which are considered difficult to be producedfor FZ wafers. Furthermore, since COPs are reduced for the whole crystal(whole wafer), the stock removal of the delaminated plane for polishingis not required to be limited, when the delaminated wafer is recycled asa bond wafer.

Further, by subjecting an SOI wafer produced as described above, inwhich COPs in the SOI layer are reduced, to a heat treatment under anatmosphere containing hydrogen or argon in a batch processing typefurnace, the surface roughness of the SOI layer can be reduced withoutproducing pits of the buried oxide layer.

According to the present invention, there is further provided an SOIwafer which is produced by the aforementioned method, characterized inthat the wafer has an RMS (root mean square roughness) value of 0.5 nmor less concerning surface roughness for both of 1 μm square and 10 μmsquare.

Thus, in the SOI wafer produced according to the present invention,although it is produced without polishing, both of the short periodcomponents (for example, about 1 μm square) and the long periodcomponents (for example, about 10 μm square) of the surface roughness ofthe SOI layer are improved, and both of RMS values therefor are verysmall, i.e., 0.5 nm or less, which means surface roughness comparable tothat of mirror-polished wafers. In addition, the film thickness does notbecome uneven unlike in a case where the surface is polished. Therefore,such an SOI wafer can suitably be used for the production of recenthighly integrated devices.

As explained above, in the method for producing an SOI wafer of thepresent invention, by subjecting a wafer having an SOI layer to atwo-stage heat treatment utilizing a rapid heating/rapid coolingapparatus and a batch processing type furnace in an atmospherecontaining hydrogen or argon after the delamination step, both of shortperiod components and long period components of surface roughness ofdelaminated plane of the wafer can be markedly improved. Further,crystallinity is also restored, and pits due to COPs in the bond waferto be used are not generated.

Furthermore, the short period components of surface roughness areimproved within an extremely short period of time by the heat treatmentusing an RTA apparatus, and in addition, a lot of wafers can beprocessed at one time and the long period components are improved in abatch processing type furnace. Therefore, the heat treatment can beefficiently performed as a whole, and thus SOI wafers of superiorsurface characteristics can be produced at a low cost.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1(a) to (h) show a flow diagram of an exemplary process forproducing an SOI wafer by the hydrogen ion delamination method accordingto the present invention.

FIG. 2 shows a graph representing relationship among RTA treatmenttemperature, treatment time, and P-V value for 1 μm square.

FIG. 3 shows a graph representing relationship among RTA treatmenttemperature, treatment time, and P-V value for 10 μm square.

FIG. 4 shows a graph representing relationship among RTA treatmenttemperature, treatment time, and RMS value for 1 μm square.

FIG. 5 shows a graph representing relationship among RTA treatmenttemperature, treatment time, and RMS value for 10 μm square.

FIG. 6 is a schematic view showing an exemplary rapid heating/rapidcooling apparatus.

FIG. 7 is a schematic view showing another exemplary rapid heating/rapidcooling apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereafter, embodiments of the present invention will be explained withreference to the appended drawings. However, the present invention isnot limited to these.

FIG. 1 shows a flow diagram of an exemplary process for producing an SOIwafer by the hydrogen ion delamination method according to the presentinvention.

The present invention will be explained hereafter mainly as for a casewhere two of silicon wafers are bonded.

In the hydrogen ion delamination method shown in FIG. 1, twomirror-surface silicon wafers are prepared first in the step (a). Thatis, a base wafer 1 that serves as a substrate and a bond wafer 2 fromwhich an SOI layer is obtained, which correspond to specifications ofdevices, are prepared.

Then, in the step (b), at least one of the wafers, the bond wafer 2 inthis case, is subjected to thermal oxidation to form an oxide layer 3having a thickness of about 0.1-2.0 μm on its surface.

In the step (c), at least either hydrogen ions or rare gas ions,hydrogen ions in this case, are implanted into one surface of the bondwafer 2 on which surface the oxide layer was formed to form a microbubble layer (enclosed layer) 4 parallel to the surface in meanpenetrating depth of the ions. The ion implantation temperature ispreferably 25-450° C.

The step (d) is a step of superimposing the base wafer 1 on the hydrogenion-implanted surface of the hydrogen ion implanted bond wafer 2 via anoxide layer and bonding them. By contacting the surfaces of two of thewafers to each other in a clean atmosphere at an ordinary temperature,the wafers are adhered to each other without using an adhesive or thelike.

The subsequent step (e) is a delamination heat treatment step in whichthe wafers were delaminated at the enclosed layer 4 as a border toseparate them into a delaminated wafer 5 and a wafer 6 having an SOIlayer (SOI layer 7+buried oxide layer 3+base wafer 1). For example, ifthe wafers are subjected to a heat treatment at a temperature of about500° C. or more under an inert gas atmosphere, the wafers are separatedinto the delaminated wafer 5 and the wafer 6 having an SOI layer due torearrangement of crystals and aggregation of bubbles (this wafer may besimply called SOI wafer hereinafter including such a wafer subjected toa heat treatment).

As for the steps thus far, the method of the present invention is thesame as the conventional hydrogen ion delamination method. And in thepresent invention, the method is characterized by subjecting the wafer 6having an SOI layer 7 to a two-stage heat treatment in an atmospherecontaining hydrogen or argon using a rapid heating/rapid coolingapparatus and a batch processing type furnace (step (g)), after thedelamination heat treatment step (e). In this case, the atmospherecontaining hydrogen or argon may consist of 100% of hydrogen, 100% ofargon or a mixed gas of hydrogen and argon.

In addition, after the delamination heat treatment step (e) and beforeperforming the two-stage heat treatment step (g), the bonding heattreatment may be performed in the step (f) like a conventional method.Since the bonding strength of the wafers brought into close contact inthe aforementioned bonding step (d) and the delamination heat treatmentstep (e) as it is would be weak for use in the device productionprocess, the wafer 6 having an SOI layer is subjected to a heattreatment at a high temperature as a bonding heat treatment in this step(f) to obtain sufficient bonding strength. This heat treatment ispreferably performed, for example, at 1050° C. to 1200° C. for 30minutes to 2 hours under an inert gas atmosphere.

In the present invention, after the delamination heat treatment step(e), the wafer 6 having an SOI layer is subjected to the bonding heattreatment as required, and then subjected to the two-stage heattreatment in an atmosphere containing hydrogen or argon using a rapidheating/rapid cooling apparatus and a batch processing type furnace. Inthis case, since it is inefficient to separately perform the bondingheat treatment (step (f)) and the two-stage heat treatment, thetwo-stage heat treatment using a rapid heating/rapid cooling apparatusand a batch processing type furnace according to the present inventionmay also serve as the bonding heat treatment.

As for the order of the heat treatment using a rapid heating/rapidcooling apparatus and the heat treatment using a batch processing typefurnace, the heat treatment using a rapid heating/rapid coolingapparatus is preferably performed first, in particular, when a usual CZwafer having a lot of COPs is used as a bond wafer.

This is because of the following reasons. A CZ wafer contains COPsintroduced during the crystal production as described above. Therefore,when the SOI layer is thin as required in recent years, the COPs mayexist while penetrating the SOI layer to form pinholes. In such a case,if the wafer is subjected to a heat treatment in an atmospherecontaining hydrogen or argon over a long period of time in a batchprocessing type furnace, hydrogen gas or argon gas may penetrate throughthe pinholes and etch the buried oxide layer 3 to form pits during theheat treatment.

Therefore, when a usual CZ wafer is used as the bond wafer, if the heattreatment by the rapid heating/rapid cooling apparatus is performedfirst to improve the short period components of surface roughness andsimultaneously restore the surface crystallinity to markedly reduce COPsin the SOI layer, and then the heat treatment is performed in the batchprocessing type furnace for a relatively long period of time to improvethe long period components, both of the short period components and longperiod components of surface roughness will be improved, and possibilityof the generation of pits will also be eliminated.

On the other hand, if an epitaxial wafer, FZ wafer or CZ wafer of whichCOPs at least on surface are reduced is used as the bond wafer, theaforementioned problem of the etching of the buried oxide layer is notcaused. Therefore, either of the heat treatments may be performed firstin principle, and it also becomes possible to perform the heat treatmentat a high temperature for a long period of time by using only a batchprocessing type furnace, while omitting the heat treatment using a rapidheating/rapid cooling apparatus.

That is, if the material of the bond wafer is suitably selected, an SOIwafer excellent in both of the short period components and long periodcomponents of surface roughness can be obtained by subjecting the waferto a heat treatment at a temperature of about 1000-1300° C. for 10minutes to about 5 hours in a batch processing type furnace, whileavoiding the problem of etching of the buried oxide layer, as in thecase of performing the two-stage heat treatment.

Examples of the CZ wafer of which COPs at least on surface are reducedinclude a CZ wafer produced from a single crystal ingot of which COPsare reduced for the whole crystal by changing a usual CZ single crystalpulling rate (about 1 mm/min) to a pulling rate of, for example, 0.6mm/min or lower, a CZ wafer produced from a single crystal ingot ofwhich grown-in defects such as COPs are reduced for the whole crystal bycontrolling V/G (V: pulling rate, G: temperature gradient along thedirection of solid-liquid interface of crystal), or a CZ wafer producedwith usual pulling conditions and subjected to a heat treatment in anatmosphere of hydrogen, argon or the like to reduce COPs contained in atleast a region of wafer surface to be an SOI layer, and so forth.

Through the aforementioned steps (a) to (g), there can be obtained anSOI wafer 6 of high quality, in which both of the long period componentsand short period components of surface roughness are improved, and whichhas an SOI layer 7 of high crystal quality and high thickness uniformityand shows no pit formation (step (h)).

Further, by selecting a CZ wafer produced from a single crystal ingot ofwhich COPs are reduced for the whole crystal as the CZ wafer of whichCOPs at least on surface are reduced, the following remarkableadvantages can be obtained.

That is, it is considered that, as a bond wafer for producing an SOIwafer of which COPs in the SOI layer are reduced compared with an SOIwafer produced by using a CZ wafer produced under the usual crystalpulling conditions, besides use of a CZ wafer produced from a singlecrystal ingot of which COPs are reduced for the whole crystal, anepitaxial wafer, FZ wafer or CZ wafer subjected to hydrogen (argon)annealing may be used.

However, in the case of epitaxial wafer, an epitaxial layer is depositedon a surface of usual mirror-polished wafer, and its surface roughness(haze level) is degraded compared with a usual mirror-polished surface.Furthermore, projections called mounds and the like may be generated onthe surface. Therefore, if such a surface is bonded, bonding failurescalled voids or blisters are likely to occur due to the influence of thedegraded surface roughness: or protrusions. Therefore, there may be useda measure of slightly polishing the epitaxial layer and then using itfor bonding.

On the other hand, in the case of a CZ wafer produced from a singlecrystal ingot of which COPs are reduced for the whole crystal, since amirror-polished surface of a mirror-surface wafer sliced from the singlecrystal and processed can be used as it is, the bonding failures can bereduced compared with an epitaxial wafer.

Further, when the bond wafer after the delamination is recycled as abond wafer, the delaminated plane must be polished before use. However,an epitaxial wafer suffers from a problem that, if the stock removal forpolishing becomes large, the epitaxial layer may be removed. Therefore,it is necessary to take a countermeasure such as depositing theepitaxial layer with a sufficiently large thickness beforehand or makingthe stock removal for polishing small. This problem is similarly appliedto a wafer of which COPs are reduced only in the vicinity of the wafersurface, like a CZ wafer subjected to hydrogen (argon) annealing.

In contrast, in the case of a CZ wafer produced from a single crystalingot of which COPs are reduced for the whole crystal, since COPs arereduced for the whole wafer, the stock removal for polishing is notlimited for recycling at all, and the wafer can be recycled for aplurality of times.

Further, a CZ wafer produced from a single crystal ingot of which COPsare reduced for the whole crystal is advantageous in view of thepossibility of the production of wafers having a larger diameter. As forFZ wafers, the maximum diameter of wafers currently produced oncommercial level is 150 mm, and it is extremely difficult to obtainwafers having a diameter of 200 mm, 300 mm or a further larger diameter.As for CZ wafers, on the other hand, those having a diameter of 300 mmare already mass-produced, and study for production of those having afurther larger diameter is also progressing. Therefore, it is wellpossible to meet the demand for a larger diameter.

As described above, the production of SOI wafers by the hydrogen iondelamination method using CZ wafers produced from a single crystal ingotof which COPs are reduced for the whole crystal as bond wafers is theonly method that simultaneously has three kinds of advantages, i.e.,reduction of bonding failures, reuse of bond wafers and usability forwafers of a large diameter.

The two-stage heat treatment performed in the present invention will beexplained in more detail hereafter.

First, the heat treatment performed in an atmosphere containing hydrogenor argon using a rapid heating/rapid cooling apparatus can be performedin a temperature range of 1000° C. to the melting point or lower ofsilicon for 1-300 seconds.

By subjecting a wafer having an SOI layer after the delamination to aheat treatment in an atmosphere containing hydrogen or argon using arapid heating/rapid cooling apparatus, crystallinity of the SOI layersurface can be efficiently restored in an extremely short period oftime, surface roughness, in particular, short period components thereof(about 1 μm square) can be improved, and COPs in the SOI layer can alsobe markedly reduced. The heat treatment can be performed moreeffectively in a temperature range of 1200-1350° C.

Examples of such an apparatus that can rapidly heat and rapidly cool anSOI wafer in an atmosphere containing hydrogen or argon, which is usedin the present invention, include apparatuses such as lamp heaters basedon heat radiation. As an example of commercially available apparatuses,SHS-2800 produced by AST Corp. can be mentioned. These apparatuses arenot particularly complicated, and are not expensive either.

An example of apparatus that can rapidly heat and rapidly cool a waferhaving an SOI layer in an atmosphere containing hydrogen or argon, whichis used in the present invention, will be explained hereinafter. FIG. 6is a schematic view of an apparatus capable of rapid heating and rapidcooling.

The heat treatment apparatus 20 shown in FIG. 6 has a bell jar 21composed of, for example, silicon carbide or quartz, and a wafer isheat-treated in this bell jar 21. Heating is performed by heaters 22 and22′, which are disposed so that they should surround the bell jar 21.These heaters are each constituted by an upper heater and a lower heaterwhich are separated from each other, so that electric power supplied toeach of them can be independently controlled. Of course, the heatingmechanism is not limited to this, and the so-called radiant heating,radiofrequency heating and so forth may also be used. A housing 23 forshielding heat is disposed outside the heaters 22 and 22′.

A water cooled chamber 24 and a base plate 25 are disposed under afurnace, and they shut the inside of the bell jar 21 off from the outerair. An SOI wafer 28 is held on a stage 27, and the stage 27 is fixed atthe top of supporting shaft 26, which can be freely moved upward anddownward by a motor 29. The water cooled chamber 24 has a waferinsertion port (not shown in the figure) which can be opened and closedby a gate valve, so that the wafer can be loaded into and unloaded fromthe furnace along the transverse direction. The base plate 25 isprovided with a gas inlet and exhaust outlet, so that the gaseousatmosphere in the furnace can be controlled.

By using such a heat treatment apparatus 20 as mentioned above, the heattreatment of an SOI wafer for rapid heating and rapid cooling in anatmosphere containing hydrogen or argon is performed as follows.

First, the inside of the bell jar 21 is heated to a desired temperature,for example, 1000° C. to the melting point of silicon, by the heaters 22and 22′, and maintained at that temperature. By independentlycontrolling the electric power supplied to each of the separate heaters,temperature profile can be obtained in the bell jar 21 along its heightdirection. Therefore, the heat treatment temperature can be selected bychanging the position of the stage 27, i.e., the length of thesupporting shaft 26 inserted into the furnace. The atmosphere for theheat treatment is controlled by introducing an atmospheric gascontaining hydrogen or argon through a gas inlet of a base plate 25.

After the inside of the bell jar 21 is maintained at the desiredtemperature, an SOI wafer is inserted from the insertion port of thewater cooled chamber 24 by a wafer handling apparatus not shown in thefigure, which is disposed at an adjacent position of the heat treatmentapparatus 20, and placed on the stage 27 waiting at its lowest positionvia, for example, a SiC boat etc. At this point, because the watercooled chamber 24 and the base plate 25 are cooled with water, the waferis not heated to a high temperature at that position.

After the SOI wafer is placed on the stage 27, the stage 27 isimmediately elevated to a position of desired temperature of from 1000°C. to the melting point of silicon by inserting the supporting shaft 26into the inside of the furnace by the motor 29 so that the SOI wafer onthe stage should be subjected to the high temperature heat treatment. Inthis operation, because the stage moves from its lowest position in thewater cooled chamber 24 to the desired temperature position within, forexample, only 20 seconds, the SOI wafer will be rapidly heated.

Then, by maintaining the stage 27 at the desired temperature positionfor a predetermined period of time (for example, 1-300 seconds), thewafer having an SOI layer can be subjected to the high temperature heattreatment in an atmosphere containing hydrogen or argon for the timethat the wafer is maintained at the heating position. When thepredetermined time has passed and the high temperature heat treatmentwas finished, the stage 27 is immediately descended by pulling thesupporting shaft 26 out from the furnace by the motor 29, and positionedat the bottom of the water cooled chamber 24. This descending operationcan also be performed within, for example, about 20 seconds. Because thewater cooled chamber 24 and the base plate 25 are cooled with water, thewafer having an SOI layer on the stage 27 is cooled rapidly. Finally,the SOI wafer is unloaded by the wafer handling apparatus to finish theheat treatment.

When additional SOI wafers are to be heat-treated, those wafers can beintroduced successively into the apparatus and subjected to the heattreatment, since the temperature in the heat treatment apparatus 20 isnot lowered.

Another example of the rapid heating/rapid cooling apparatus (RTAapparatus) for SOI wafers used in the present invention will beexplained hereafter.

The heat treatment apparatus 30 shown in FIG. 7 has a chamber 31consisting of quartz, and a wafer 38 is heat-treated within this chamber31. Heating is achieved by heating lamps 32, which are disposed underand over the chamber and at left and right of the chamber so that theyshould surround the chamber 31. Electric power supplied to these lamps32 can be independently controlled.

An auto shutter 33 is provided at the gas exhausting side, and it shutsthe inside of the chamber 31 off from the outer air. The auto shutter 33has a wafer loading port not shown in the figure, which can be openedand closed by a gate valve. The auto shutter 33 is also provided with agas exhausting outlet, so that the atmosphere in the furnace can becontrolled.

The wafer 38 is placed on a three-point supporting part 35 formed on aquartz tray 34. A buffer 36 made of quartz is provided at the gas inletside of the tray 34, so that it can prevent the wafer 38 from beingdirectly blown by the introduced gas flow.

Further, the chamber 31 is provided with a special window fortemperature measurement, which is not shown in the figure, and thetemperature of the wafer 38 can be measured by a pyrometer 37 installedin the outside of the chamber 31 through the special window.

By using the heat treatment apparatus 30 mentioned above, the heattreatment for rapid heating and rapid cooling of a wafer is performed asfollows.

First, the wafer 38 is loaded into the chamber 31 from the loading portand placed on the tray 34 by a wafer handling apparatus disposed at anadjacent position of the heat treatment apparatus 30 but not shown inthe figure. Then, the auto shutter 33 is closed.

Subsequently, electric power is supplied to the heating lamps 32 to heatthe wafer 38 to a predetermined temperature, for example, 1100° C. to1300° C. In this operation, it takes, for example, about 20 seconds toattain the desired temperature. Then, the wafer 38 is maintained at thetemperature for a predetermined period of time, and thus the wafer 38can be subjected to a high temperature heat treatment. When thepredetermined time has passed and the high temperature heat treatment isfinished, output of the lamps is reduced to lower the temperature of thewafer. This temperature decrease can be also performed within, forexample, about 20 seconds. Finally, the wafer 38 is unloaded by thewafer handling apparatus to finish the heat treatment.

As explained above, the heat treatment by using a rapid heating/rapidcooling apparatus (RTA apparatus) according to the present inventioninclude a method utilizing such an apparatus as shown in FIG. 6, whereina wafer is immediately loaded into a heat treatment furnace set at atemperature within the aforementioned temperature range, and the waferis immediately unloaded after the aforementioned heat treatment time haspassed, a method utilizing such an apparatus as shown in FIG. 7, whereina wafer is placed at a predetermined position in a heat treatmentfurnace and immediately heated by lamp heaters or the like, and soforth. The expressions of “to immediately load” and “to immediatelyunload” mean that there are not employed the conventional temperatureincreasing and decreasing operations performed over a certain period oftime and the so-called loading and unloading operations in which wafersare slowly loaded into and unloaded from a heat treatment furnace. Ofcourse, however, it takes a certain short period of time to transportthe wafer to the predetermined position in the furnace, and it takesseveral seconds to several minutes depending on the performance of atransportation apparatus for loading a wafer.

When the heat treatment is performed by using such a heat treatmentapparatus as shown in FIG. 6 or 7, the atmosphere for the heat treatmentin an atmosphere containing hydrogen or argon according to the presentinvention may be, for example, 100% hydrogen atmosphere, 100% argonatmosphere or a mixed gas atmosphere of hydrogen and argon.

If such a heat treatment atmosphere is used, crystallinity of a damagedlayer of SOI wafer surface is surely restored and surface roughness, inparticular, short period components thereof, can be improved withoutforming a harmful coated film on the SOI wafer surface.

Among the heat treatments constituting the two-stage heat treatmentperformed in the present invention, the heat treatment performed in anatmosphere containing hydrogen or argon by using a batch processing typefurnace will be explained hereafter.

The term “batch processing type furnace” used herein means a so-calledbatch type heat treatment furnace of, usually, vertical type orhorizontal type, in which a plurality of wafers are placed, hydrogen gasis introduced, temperature is relatively slowly elevated to subject thewafers to a heat treatment at a predetermined temperature forpredetermined time, and the temperature is relatively slowly lowered.Such an apparatus is capable of heat treatment of a large number ofwafers at one time. Such an apparatus is also excellent in thecontrollability of temperature, and hence enables stable operation.

The heat treatment conditions for the batch processing type furnace arebasically the same as those for the aforementioned RTA apparatus exceptthat the heat treatment time becomes longer. It can be performed in 100%hydrogen atmosphere, 100% argon atmosphere or a mixed gas atmosphere ofhydrogen and argon at a temperature of from 1000° C. to the meltingpoint of silicon, and in particular, it can be performed moreeffectively at a temperature range of 1200-1350° C.

By performing a heat treatment in an atmosphere containing hydrogen orargon using a batch processing type furnace as described above, the longperiod components (for example, about 10 μm square) of surface roughnessof SOI wafer can be improved. In particular, if the heat treatment usingthe aforementioned batch processing type furnaces is performed after theheat treatment using the aforementioned rapid heating/rapid coolingapparatus, surface roughness of SOI wafers can be improved over therange from short period to long period, and SOI wafers free from pitsgenerated due to COPs can be obtained, even if CZ wafers are used asbond wafers.

Further, compared with the treatment method by using only the rapidheating/rapid cooling apparatus for a long period of time, the heattreatment can be performed more efficiently, and SOI wafers excellent inthe surface characteristics can be produced with a high throughput at alow cost.

The SOI wafer of the present invention produced as described above canbe an SOI wafer of which both of RMS values for 1 μm square and 10 μmsquare concerning surface roughness are 0.5 nm or less.

The SOI wafer of the present invention, of which both of RMS values for1 μm square and 10 μm square concerning surface roughness are 0.5 nm orless as described above, has surface roughness substantially comparativeto that of mirror-polished wafers over the range from short period tolong period and is excellent in the film thickness uniformity.Therefore, it can be preferably used for the production of recent highlyintegrated devices.

The present invention will be specifically explained with reference toheat treatment tests according to the present invention as well asexamples and comparative examples. However, the present invention is notlimited to these.

<Heat treatment test using RTA apparatus>

Production of SOI wafers:

First, using a base wafer 1 and a bond wafer 2, both of which weremirror surface silicon wafers produced by the CZ method and having adiameter of 150 mm, a wafer 6 having an SOI layer was obtained throughdelamination of the bond wafer 2 according to the steps (a) to (e) shownin FIG. 1. In this production, thickness of the SOI layer 7 was made tobe 0.4 μm, and the other major conditions including those for the ionimplantation were as follows.

1) Thickness of buried oxide layer: 400 nm (0.4 μm)

2) Hydrogen implantation conditions: H⁺ions, implantation energy: 100keV, implantation dose: 8 ×10¹⁶/cm²

3) Delamination heat treatment conditions: in N₂ gas atmosphere, 500 °C., 30 minutes

In this way, the wafer 6 having an SOI layer 7 with a thickness of about0.4 μm was obtained.

Measurement of surface roughness:

First, as for surface roughness of a delaminated wafer as it is obtainedin FIG. 1(e), i.e., a wafer having an SOI layer not subjected to thetwo-stage heat treatment according to the present invention at all, P-V(Peak to Valley) value and RMS value of its surface (delaminated plane)were measured by atomic force microscopy for 1 μm square and 10 μmsquare. The P-V values were 56.53 nm in average for 1 μm square, and56.63 nm in average for 10 μm square. The RMS (root mean squareroughness) values were 7.21 nm in average for 1 μm square, and 5.50 nmin average for 10 μm square.

Subsequently, the wafer having an SOI layer obtained through theaforementioned steps of (a) to (e) shown in FIG. 1 was subjected to anRTA treatment in a temperature range of 1000° C. to 1225° C. in anatmosphere containing hydrogen, and then its surface roughness in termsof P-V value and RMS value was measured for 1 μm square and 10 μm squareby atomic force microscopy.

The results of the above measurement are shown in graphs of FIGS. 2-5.

FIG. 2 shows a graph representing relationship among the RTA treatmenttemperature, the treatment time and the P-V value for 1 μm square. Thisgraph shows that the RTA treatment in a temperature range of 1000° C. to1225° C. for several seconds to several tens of seconds greatly improvedthe short period components (1 μm) of surface roughness compared withthe untreated one, and provided P-V values comparable to that of amirror-polished wafer (PW). In FIG. 2, values corresponding to thetemperatures of 1000, 1100, 1200 and 1225° C. are plotted with squares,triangles, rhomboids and circles, respectively.

FIG. 3 shows a graph representing relationship among the RTA treatmenttemperature, the treatment time and the P-V value for 10 μm square. Itcan be seen that the long period components (10 μm) of surface roughnesswere gradually improved as the treatment time became longer, unlike thecase of the aforementioned short period components, and, to obtain a P-Vvalue comparable to that of a mirror-polished wafer (PW), although itdepended on the treatment temperature, a period of around severalthousands of seconds was required even when the treatment was performedat, for example, 1225° C.

FIGS. 4 and 5 show the measurement results for the short periodcomponents (1 μm) and the long period components (10 μm) of surfaceroughness in terms of RMS values, respectively, and they showrelationship among the RTA treatment temperature, the treatment time andthe RMS value.

From the results shown in the graph of FIG. 4, it can be seen that,although the RMS value decreased by the RTA treatment at 1200° C. as thetreatment time became longer and the surface roughness tended to beimproved with time, the RMS value was markedly improved to a level of amirror-polished wafer (PW) by the RTA treatment for several seconds orseveral tens of seconds at any temperature. The relationship of thesymbols used for the plotting and the temperatures in FIG. 4 is similarto that in FIG. 2.

On the other hand, as for the long period components of surfaceroughness, unlike the case of the aforementioned short periodcomponents, they were gradually improved as the treatment time becamelonger as evident from the graph of FIG. 5, and, to obtain an RMS valuecomparable to that of a mirror-polished wafer (PW), although it dependedon the treatment temperature, it can be seen that a period of aroundseveral thousands of seconds was required even when the treatment wasperformed at, for example, 1225° C.

From the above results, it can be seen that the short period components(about 1 μm) of surface roughness are greatly improved to a levelcomparable to that of a mirror-polished wafer by the RTA treatment foran extremely short period of time (several seconds or several tens ofseconds), whereas the long period components (about 10 μm) cannot bemade to be at a level comparable to that of a mirror-polished wafer,although it depends on the treatment temperature, unless the heattreatment is performed for a long period of time (several thousands ofseconds or more).

EXAMPLES 1 AND 2 AND COMPARATIVE EXAMPLE 1

Heat treatment of SOI wafers:

An SOI wafer produced under the same condition as the SOI wafer used forthe aforementioned heat treatment test using the RTA apparatus accordingto the steps (a) to (e) shown in FIG. 1 was subjected to a heattreatment by an RTA apparatus under each of the conditions shown inTable 1 (100% hydrogen atmosphere), and then subjected to a heattreatment by a batch processing type furnace (100% argon atmosphere) toobtain an SOI wafer, which was subjected to the two-stage heat treatmentaccording to the present invention (Examples 1 and 2). Separately, therewas also prepared a wafer subjected to the heat treatment by the RTAapparatus but not subjected to the heat treatment by the batchprocessing type furnace thereafter

COMPARATIVE EXAMPLE 1

TABLE 1 Heat Heat treatment by treatment Heat treatment by batchprocessing condition RTA apparatus type furnace Example 1 1225° C., 10seconds 1200° C., 1 hour Example 2 1200° C., 30 seconds 1200° C., 1 hourComparative 1225° C., 10 seconds None Example 1Surface roughness measurement:

Surface roughness (RMS value) of the SOI wafers obtained in theaforementioned Examples 1 and 2 and Comparative Example 1 was measuredbefore and after the heat treatment by atomic force microscopy for 1 μmsquare and 10 μm square, and the results are shown in Table 2.

TABLE 2 Before heat After heat Results of treatment treatment surface(RMS: nm) (RMS: nm) roughness 1 μm 10 μm 1 μm 10 μm measurement squaresquare square square Example 1 7.21 5.50 0.18 0.28 Example 2 7.50 5.800.20 0.30 Comparative 7.45 5.75 0.21 1.60 Example 1

As clearly seen from the results shown in Table 2, substantially nodifference of the RMS values before the heat treatment was seen amongthe wafers for both of 1 μm square and 10 μm square.

On the other hand, after the heat treatment, although there was almostno difference of the values among the wafers for 1 μm square, the valuesfor 10 μm square of the wafers of Examples 1 and 2 were greatly improvedto a level near their RMS values for 1 μm square. However, as for thewafer of Comparative Example 1, which was not subjected to the heattreatment by the batch processing type furnace, the RMS value for 1 μmsquare was greatly improved, whereas the RMS value for 10 μm square wassignificantly larger than those of the wafers of Examples 1 and 2, andthus it can be seen that the long period components of surface roughnesswere not improved sufficiently.

EXAMPLES 3 AND 4

Production of bond wafers:

A silicon single crystal ingot was produced by the CZ method withapplying a magnetic field, in which the pulling condition (V/G) wascontrolled to reduce grown-in defects in the crystal. This ingot wasprocessed in a conventional manner to produce a mirror-surface CZ wafer(diameter: 200 mm, crystal orientation <100>) of which COPs were reducedfor the whole crystal (Example 3). COPs and haze level on the surface ofthis wafer were measured by using a surface inspection apparatus (SP-1,produced by KLA/Tencor Co., Ltd.), and it was found that no COP having adiameter of 0.12 μm or more existed on the surface and the haze level ofthe mirror surface was about 0.03 ppm in average.

Separately, a CZ mirror-surface wafer (diameter: 200 mm, crystalorientation <100>), which was produced from a silicon single crystalingot pulled with usual pulling condition (pulling rate: 1.2 mm/min),was loaded into an epitaxial growth apparatus to produce an epitaxialwafer having an epitaxial layer with a thickness of 10 μm at 1125° C.(Example 4).

The number of COPs having a diameter of 0.12 μm or more existing on theCZ wafer surface before the deposition of the epitaxial layer was about1000 per wafer in average. Haze level of the epitaxial layer surface wasabout 0.2 ppm in average. There also was a wafer having projectionscalled mounds.

Production of SOI wafers:

Ten wafers for each of the wafers produced as bond wafers by the methodsof the aforementioned Example 3 and Example 4 were prepared, and SOIwafers were produced under the same conditions as the aforementionedheat treatment test by the RTA apparatus according to the steps (a) to(e) shown in FIG. 1. By inspecting the SOI surfaces and bonding surfacesafter the delamination, existence of voids or blisters was investigatedand cause of their generation was examined. As a result, it wasconfirmed that no void considered to be generated due to the haze orprotrusions of the bond wafer surfaces (bonding surfaces) was observedat all for the SOI wafers produced by using the wafers of Example 3,whereas voids or blisters considered to be generated due to haze ormounds on the epitaxial layer surfaces were present on three SOI wafersof ten SOI wafers produced by using the wafers of Example 4.

Heat treatment of SOI wafers:

The aforementioned SOI wafers of Example 3 and Example 4 after thedelamination were subjected to a heat treatment at 1225° C. for 3 hoursby using a batch processing type furnace in an atmosphere of 97%argon/3% hydrogen, without polishing the SOI layer surfaces.

Surface roughness measurement:

The surface roughness of the aforementioned SOI wafers obtained inExamples 3 and 4 was measured for 1 μm square and 10 μm square beforeand after the heat treatment. The results are shown in Table 3.

TABLE 3 Before heat After heat treatment (RMS: nm) treatment (RMS: nm) 1μm 10 μm 1 μm 10 μm square square square square Example 3 7.33 5.60 0.180.33 Example 4 7.42 5.73 0.19 0.35

While the present invention was explained above with reference to theexamples, the present invention is not limited to the embodimentsdescribed above. The above-described embodiments are mere examples, andthose having the substantially same structure as that described in theappended claims and providing the similar functions and advantages areincluded in the scope of the present invention.

For example, while CZ wafers and epitaxial wafers were used in theaforementioned examples, wafers that can be used in the presentinvention are not limited to those, and FZ wafers and hydrogen (argon)annealed wafers can also be used.

Further, while the present invention was explained above mainly for thecases of bonding two of semiconductor wafers (silicon wafers), thepresent invention is not limited to those, and can similarly be appliedto cases where a semiconductor wafer and an insulating substrate (forexample, substrates of quartz, sapphire, alumina etc.) are directlybonded to produce SOI wafers.

1. A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected, in an atmosphere containing hydrogen or argon, to both a heat treatment utilizing a rapid heating/rapid cooling apparatus to improve the surface roughness of short periods of the SOI layer and a heat treatment utilizing a batch processing type furnace to improve the surface roughness of long periods of the SOI layer.
 2. The method for producing an SOI wafer according to claim 1, wherein the two-stage heat treatment is performed by subjecting the wafers to a heat treatment in the rapid heating/rapid cooling apparatus and then a heat treatment in the batch processing type furnace.
 3. A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein an FZ wafer, an epitaxial wafer or a CZ wafer of which COPs at least on surface are reduced is used as the bond wafer, and the wafer having an SOI layer is subjected to a heat treatment under an atmosphere containing hydrogen or argon in a batch processing type furnace after the delamination step. 